LED Matrix Driver / Documentation
LED Matrix Driver, in detail
A 128×64 RGB LED panel driver in SystemVerilog on an iCE40
Project brief
A SystemVerilog driver for a custom 128×64 RGB LED matrix on a Lattice iCE40UP5K. An STM32 sends frames over SPI. The FPGA double-buffers them, applies gamma correction, and drives the panel with 8-bit binary code modulation at 120 Hz or more, with global dimming.
The design passes all of its simulation and synthesis checks: 9 of 9 cocotb tests, a 121.7 Hz refresh, and timing closed at 39 MHz against a 33 MHz target, using 16% of the chip. It hasn’t run on real hardware yet. The board it will run on is drawn as a schematic, with the layout still to do.
What’s included
• 8-bit binary code modulation at 120 Hz or higher, with global dimming
• Double-buffered frames streamed over SPI from an STM32
• cocotb testbenches checked against a Python model of the panel
• An all open-source toolchain: yosys, nextpnr-ice40, icestorm and Verilator
Current status
This is a prototype. This page describes where it’s headed now. It doesn’t promise general availability.
Questions and support
For questions about LED Matrix Driver, contact DWMM Holdings with the project name and a short description of what you need. Please don’t send credentials or other sensitive information by email.