LED Matrix Driver Get in touch

Specified · Hardware and firmware

LED Matrix Driver

A 128×64 RGB panel driven from an iCE40 — the timing worked out in SystemVerilog, not guessed.

FPGA engineers who want the refresh, gamma and BCM described rather than demonstrated.

Animated illustration of LED Matrix Driver LED Matrix Driver — mechanism STATE SYSTEMVERILOG · ICE40 · COCOTB · PYTHON
Animated schematic of the core mechanism, drawn from the written design.
Built on
SystemVerilog + iCE40
No vendor code
Every layer in the build is one you can read
History
1 commit, in a private repository

What it is

A SystemVerilog driver for a custom 128×64 RGB LED matrix on a Lattice iCE40UP5K. An STM32 streams frames over SPI; the FPGA double-buffers them, applies gamma correction, and drives the panel with 8-bit binary code modulation at 120 Hz or better, with global dimming.

The repository carries the timing and multiplexing analysis, cocotb testbenches with a Python reference oracle, and the full open-source build flow — yosys, nextpnr and icestorm.

Capabilities

What it actually does.

FPGA engineers who want the refresh, gamma and BCM described rather than demonstrated.

  1. 8-bit binary code

    8-bit binary code modulation at ≥120 Hz refresh with global dimming

  2. Double-buffered frame ingest

    Double-buffered frame ingest over SPI from an STM32

  3. cocotb testbenches

    cocotb testbenches with a Python panel model as the reference oracle

  4. Fully open-source toolchain

    Fully open-source toolchain: yosys, nextpnr-ice40, icestorm, Verilator

How it works

3 moves, end to end.

This is how LED Matrix Driver works, not a set of steps you can follow yet — it is specified and not distributed.

  1. Start from the platform

    The build has no generated vendor code in it, so the first layer is already readable.

  2. Bring up the board

    Drivers, clock tree and peripherals are hand-written and unit-testable off-target.

  3. Ship and debug it

    When something is wrong, the layer that is wrong is one you can open.

The full technical description

Specification

Made of, and made when.

Read from the repository at build time rather than typed onto a marketing page.

State
Specified
Discipline
Hardware systems
Shape
Hardware and firmware
Started
Jul 2026
Last change
Jul 2026
Commits
1
  • SystemVerilog
  • iCE40
  • cocotb
  • Python
  • yosys
  • SystemVerilog 70%
  • Python 27%
  • Makefile 3%

Next

Build on LED Matrix Driver

Ask about licensing the platform, a board bring-up, or contract firmware work.

This is a pre-production site. All content is subject to finalisation, and nothing stated here is binding until the site is live.