How it works
A 128×64 RGB LED panel driver in SystemVerilog on an iCE40. The full technical description of LED Matrix Driver — what it does, what it is made of, and what state it is in.
The premise
A SystemVerilog driver for a custom 128×64 RGB LED matrix on a Lattice iCE40UP5K. An STM32 streams frames over SPI; the FPGA double-buffers them, applies gamma correction, and drives the panel with 8-bit binary code modulation at 120 Hz or better, with global dimming.
The repository carries the timing and multiplexing analysis, cocotb testbenches with a Python reference oracle, and the full open-source build flow — yosys, nextpnr and icestorm.
What is included
8-bit binary code modulation at ≥120 Hz refresh with global dimming
Double-buffered frame ingest over SPI from an STM32
cocotb testbenches with a Python panel model as the reference oracle
Fully open-source toolchain: yosys, nextpnr-ice40, icestorm, Verilator
How it is built
LED Matrix Driver is built on SystemVerilog, iCE40, cocotb, Python and yosys.
The repository is 70% SystemVerilog, 27% Python, 3% Makefile by volume — a description of what the work actually consists of rather than what it is filed under.
It carries 1 commits since Jul 2026, most recently changed in Jul 2026.
The method behind it
Every project here starts as a written specification, and the specification stays authoritative once code exists. The repository keeps a build plan with live status, an append-only decision log recording where the implementation departed from the plan, and a handoff document describing the true current state — including the parts that are not finished.
That is why a portfolio this wide is not a shallow one, and it is why this page can describe the product without overstating it.
Current state
Specified. Designed in full, build not started.
The source is private. What this page claims is checkable against the product itself, not the repository.
Next
Build on LED Matrix Driver
Ask about licensing the platform, a board bring-up, or contract firmware work.