How it works

The premise

A SystemVerilog driver for a custom 128×64 RGB LED matrix on a Lattice iCE40UP5K. An STM32 sends frames over SPI. The FPGA double-buffers them, applies gamma correction, and drives the panel with 8-bit binary code modulation at 120 Hz or more, with global dimming.

The design passes all of its simulation and synthesis checks: 9 of 9 cocotb tests, a 121.7 Hz refresh, and timing closed at 39 MHz against a 33 MHz target, using 16% of the chip. It hasn’t run on real hardware yet. The board it will run on is drawn as a schematic, with the layout still to do.

What’s included

8-bit binary code modulation at 120 Hz or higher, with global dimming

Double-buffered frames streamed over SPI from an STM32

cocotb testbenches checked against a Python model of the panel

An all open-source toolchain: yosys, nextpnr-ice40, icestorm and Verilator

How it’s built

LED Matrix Driver is built on SystemVerilog, iCE40, cocotb, Python and yosys.

The repository is 70% SystemVerilog, 27% Python, 3% Makefile by volume.

It carries 1 commits since Jul 2026, most recently changed in Jul 2026.

How the work is done

Every project here starts as a written spec, and the spec stays the source of truth once there’s code. The repository keeps a build plan with current status, an append-only decision log of where the code departed from the plan, and a handoff document that describes where things stand, including the unfinished parts.

That’s how one person keeps this many projects moving, and it’s what this page is written from.

Current state

Prototype. Works, but isn’t finished.

The source is private, so the way to check what this page says is to use the product.